Mobile Semiconductor’s silicon-proven embedded SRAM technology offers optimized TSMC 40nm, 65nm, and 55nm (with and without embedded Flash) low-power process, single-port SRAM solutions in a range of architectures:
- Low Voltage (LV)
- Ultra High Speed (UHS)
- High Density (HD)
- Multi-Megabit (MM)
Mobile Semiconductor’s proprietary design and layout techniques are applied to all architectures to optimize performance while keeping die size small.
- Low voltage (LV) SRAM and ROM use high VT devices to minimize leakage currents with limited standard VT devices used when required and a dedicated retention mode providing industry leading low standby currents. The low standby current of Mobile Semiconducotr’s LV memories are ideal for the IoT market.
- Single-port ultra-high speed (UHS) memories use low VT and standard VT devices to optimize the critical path and enhance performance while limiting static current.
- Single-port high density (HD) memories use standard VT and high VT devices to optimize the critical path and enhance performance while limiting static current.
- Single-port multi-megabit (MM) memories achieve the highest SRAM block densities with rectangular or L-shaped footprints for flexible SOC floorplanning.
TSMC 28nm, 40nm LP, TSMC 65nm LP, TSMC 55nm LP/ULP
Mobile Semiconductor’s optimized TSMC LP-process embedded single-port SRAM solutions are offered in low voltage (LV), ultra high speed (UHS), high density (HD) and multi-megabit (MM) architectures.
To ensure high manufacturing yield, the Trailblaze™ software utilizes TSMC’s standard high density 6T bit cells and is consistent with TSMC’s Design for Manufacturing (DFM) guidelines for the LP processes.
|Mobile Semiconductor Optimized TSMC 28nm HPC+Architecture||Trailblaze™ Compiler Name|
|28nm Single-Port SRAM, Low Voltage||SP-LV-TS28HPCP|
|28nm Single-Port SRAM, Low Voltage, Column Redundancy||SP-LVR-TS28HPCP|
|28nm Contact Programmable ROM, Low Voltage||ROM-ULV-TS28HPCP|
|Mobile Semiconductor Optimized TSMC 40nm LP Architecture||Trailblaze™ Compiler Name|
|40nm Single-Port, Low Voltage||SP-LV-TS40LP|
|40nm Single-Port, Ultra High Speed||SP-UHS-TS40LP|
|40nm Single-Port, High Density||SP-HD-TS40LP|
|40nm Single-Port, Multi-Megabit||SP-MM-TS40LP|
|Mobile Semiconductor Optimized TSMC 65/55nm LP Architecture||Trailblaze™ Compiler Name|
|65nm Single-Port, Low Voltage||SP-LV-TS65LP|
|55nm LP Single-Port Low Voltage SRAM||SP-LV-TS55LP|
|55nm LP Single-Port Low Voltage SRAM (Flash)||SP-LV-TS55EF|
|55nm ULP Single-Port SRAM||SP-LV-TS55ULPF|
|55nm ULP Single-Port SRAM||SP-HSLV-TS55ULPF|
|55nm ULP Single-Port ROM||ROM-LV-TS55ULPF|
|55nm ULP Single-Port (Flash)||RF1P-LV-TS55ULPF|
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