Mobile Semiconductor’s silicon-proven embedded SRAM technology offers optimized memory solutions for both TSMC and SMIC’s 40nm low-power processes. These single-port SRAM solutions are available in a range of architectures:
- Low Voltage, Low Leakage, Low Power SRAM (LV)
- Ultra High Speed SRAM (UHS)
- High Density SRAM (HD)
- Multi-Megabit SRAM (MM)
Mobile Semiconductor’s proprietary design and layout techniques are applied to all architectures to optimize performance while keeping die size small.
- Low voltage (LV) SRAM and ROM use high VT devices to minimize leakage currents with limited standard VT devices used when required and a dedicated retention mode providing industry leading low standby currents. The low standby current of Mobile Semiconductor’s LV memories are ideal for the IoT market.
- Single-port ultra-high speed (UHS) memories use low VT and standard VT devices to optimize the critical path and enhance performance while limiting static current.
- Single-port high density (HD) memories use standard VT and high VT devices to optimize the critical path and enhance performance while limiting static current.
- Single-port multi-megabit (MM) memories achieve the highest SRAM block densities with rectangular or L-shaped footprints for flexible SOC floorplanning.
TSMC 40nm LP
Mobile Semiconductor’s optimized TSMC 40nm LP-process embedded single-port SRAM solutions are offered in low voltage (LV), ultra high speed (UHS), high density (HD) and multi-megabit (MM) architectures.
To ensure high manufacturing yield, the Trailblaze™ software software utilizes TSMC’s standard high density 6T bit cells and is consistent with TSMC’s Design for Manufacturing (DFM) guidelines for the 40nm LP process.
|Mobile Semiconductor Optimized TSMC 40nm LP Architecture||Trailblaze™ Compiler Name|
|Single-Port SRAM, Low Voltage||SP-LV-TS40LP|
|Single-Port, Ultra High Speed||SP-UHS-TS40LP|
|Single-Port, High Density||SP-HD-TS40LP|
SMIC 40nm LL
Mobile Semiconductor offers an optimized SMIC 40nm LL-process embedded single-port SRAM solution in an ultra high speed (UHS) architecture.
In order to ensure high manufacturing yield, the Trailblaze™ software software utilizes SMIC’s standard high density 6T bit cells and is consistent with SMIC’s Design for Manufacturing (DFM) guidelines for the 40nm LL process.
|Mobile Semiconductor Optimized SMIC 40nm LL Architecture||Trailblaze™ Compiler Name|
|Single-Port, Ultra High Speed||SP-UHS-SM40LL|
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