65/55nm

Mobile Semiconductor’s silicon-proven embedded SRAM technology offers optimized memory solutions for both TSMC and SMIC 65nm low-power processes. These memory compilers are available in a range of architectures:

  • Low Voltage, Low Leakage, Low Power SRAM (LV)
  • Via Programmable Low Voltage, Low Power ROM (LV)
  • High Speed SRAM (HS)
  • High Density SRAM (HD)

Mobile Semiconductor’s proprietary design and layout techniques are applied to all architectures to optimize performance while keeping die size small.

  • Single-port low voltage (LV) SRAM memories use high VT devices and source biasing to minimize standby currents with limited standard VT devices used when required. This architecture provides a low power SRAM with low dynamic power, minimal peak current, and also includes a retention mode for ultra low leakage standby SRAM.
  • Single-port low power ROM instances use high VT devices with limited standard VTdevices used when required. The sub-divided bit line architecture results in low peak currents and low dynamic power. The ROM content is programmable in the via1 layer.
  • Single-port high speed (HS) memories use low VT and standard VT devices to optimize the critical path and enhance performance while limiting static current.
  • Single-port high density (HD) memories use standard VT devices to optimize the critical path and enhance performance.

TSMC 65nm LP

Mobile Semiconductor offers an optimized TSMC 65nm LP-process single-port low voltage (LV) embedded low power SRAM and ROM compilers.

To ensure high manufacturing yield, the Trailblaze™ software utilizes TSMC’s standard high density 6T bit cells and is consistent with TSMC’s Design for Manufacturing (DFM) guidelines for the 65nm LP process.

Mobile Semiconductor Optimized TSMC 65nm LP Architecture Trailblaze™ Compiler Name
Single-Port Low Voltage SRAM SP-LV-TS65LP
Low Voltage Via Programmable ROM ROM-LV-TS65LP

TSMC 55nm LP/ULP

Mobile Semiconductor offers an optimized TSMC 65nm LP-process single-port low voltage (LV) embedded SRAM solution.

To ensure high manufacturing yield, the Trailblaze™ software utilizes TSMC’s standard high density 6T bit cells and is consistent with TSMC’s Design for Manufacturing (DFM) guidelines for the 65nm LP process.

Mobile Semiconductor Optimized TSMC 55nm Architecture Trailblaze™ Compiler Name
55nm LP Single-Port LV SRAM (Flash) SP-LV-TS55LP
55nm Single-Port Low Voltage SRAM SP-LV-TS55EF
55nm ULP Single-Port, Low Voltage SRAM SP-LV-TS55ULPF
55nm ULP Single-Port, High Speed, Low Voltage ROM SP-HSLV-TS55ULPF
55nm ULP Register File, Embedded Flash RF1P-LV-TS55ULPF

GLOBALFOUNDRIES 55nm LPX

Mobile Semiconductor offers an optimized GLOBALFOUNDRIES 55nm LPX-process single-port low voltage (LV) embedded SRAM and ROM solutions.

To ensure high manufacturing yield, the Trailblaze™ software utilizes GLOBALFOUNDRIES’ standard high density 6T bit cells and is consistent with GLOBALFOUNDRIES’ Design for Manufacturing (DFM) guidelines for the 55nm LP process.

Mobile Semiconductor Optimized GLOBALFOUNDRIES 55nm LP Architecture Trailblaze™ Compiler Name
55nm LPX Dual Port, Low Voltage DP-LV-GF55LPX
55nm LPX Single-Port Register File, Low V. RF1P-LV-GF55LPX
55nm LPX Two-Port Register File, Low V. RF2P-LV-GF55LPX
55nm LPX Single-Port, Low Voltage SP-LV-GF55LPX
55nm LPX Via ROM, Low Voltage ROM-LV-GF55LPX

 

SMIC 65nm LL

Mobile Semiconductor’s optimized SMIC 65nm LL-process embedded single-port SRAM solutions are offered in high speed (HS) and high density (HD) architectures.

In order to ensure high manufacturing yield, the Trailblaze™ software utilizes SMIC’s standard high density 6T bit cells and is consistent with SMIC’s Design for Manufacturing (DFM) guidelines for the 65nm LL process.

Mobile Semiconductor Optimized SMIC 65nm LL Architecture Trailblaze™ Compiler Name
Single-Port, High Speed SRAM SP-HS-SM65LL
Single-Port, High Density SRAM SP-HD-SM65LL 

 

Custom Solutions

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