Mobile Semiconductor’s Trailblaze™ software delivers silicon-proven memory IP solutions that set the standard in high performance and low voltage embedded SRAMs.
Proven over multiple foundries with a range of technology nodes in its ability to rapidly generate memory compilers and complete memory instances, Trailblaze™ creates solutions for a broad application space.
Using standard foundry bit cells, Trailblaze™ is designed to create optimized memory compiler architectures based on the designer’s requirements including:
- low voltage, ultra high speed and high density architectures
- multiple mux options per compiler to enable various aspect ratios
- 1-bit granularity on word widths to allow for block size optimizations
- Bit Write with Global Write Enable
- Byte Write
- Column Redundancy
The optional Trailblaze™ Built-in Self Test (BIST) Compiler provides seamless integration to verify Mobile Semiconductor’s optimized, embedded SRAM solutions.
The Trailblaze™ web-based user interface provides a project management view as well as instance configuration views to allow you to rapidly and conveniently try multiple architectures and configurations
Compilers generated by the Trailblaze™ software create the necessary views to seamlessly integrate into industry-standard design flows.
EDA Views & Outputs
|GDS II Layout|
|LVS SPICE Netlist|
|Verilog RTL Wrapper|
|Verilog Test Bench|
|PDF and Text
The Trailblaze™ Built-in Self Test (BIST) Compiler provides seamless integration to verify Mobile Semiconductor’s optimized memory solutions. The configurable Trailblaze™ BIST performs at-speed testing of Trailblaze™ generated embedded SRAMs
Programmable March algorithms included in the Trailblaze™ BIST give extensive test coverage, and diagnostic capabilities provide multiple options to isolate defects.
The Trailblaze™ BIST Compiler generates a synthesizable Verilog RTL IP module as well as a top-level Verilog module to instantiate both the Trailblaze™ BIST and the Mobile Semiconductor embedded SRAM instance. Synthesis scripts are provided for enhanced design flow support.